Analysis and Performance Evaluation of 1-bit Full Adder Using Different Topologies

An adder is a digital circuit that performs addition of numbers and it plays an important role in today’s digital world. In processors and other kinds of computing devices, Adders are used in the arithmetic logic units. They are also utilized in other parts of the processors for calculating addresses, table indices, increment and decrement operations and other similar operations because it is the basic building block of on-chip libraries. Also, it can be used for the construction of many number representations and it is a trivial to modify an adder into an adder-subtractor. Full adder reduces circuit complexity and can be integrated in the calculators for addition and subtraction operations. At DSP oriented system and at networking side full adder is used mostly. Full adders can be cascaded (e.g.: ripple carry adder) easily so that one can make a cascade to add any number of bits that form the word-width of a system. In recent years, low power circuit design has been encountered as a major issue in VLSI design areas. This paper focuses on the Performance evaluation of 1-bit full adder for low power in CMOS technology using three different topologies as Static or Conventional CMOS, Gate Diffusion Input (GDI), and Hybridizing PTL (Pass Transistor Logic) techniques. This paper describes comparison of these three topologies of 1-bit full adder based on area, delay, power consumption and transistor count. Simulations are done using NgSPICE and MICROWIND DSCH tool. Keywords— CMOS Technology, Full Adder, Conventional or static logic, GDI logic, PTL, Hybridizing PTL, NMOS, PMOS, Pull up and pull down transistors, Multiplexer, sleep transistor, Xor gate, Xnor gate, SPICE, MICROWIND.